One of the main goals in technology development of semiconductor memory cells is to reduce the size of the memory cells in order to increase their density on a semiconductor wafer, thereby reducing the costs per bit. When downscaling a memory cell comprising buried bitlines, however, cross-sectional areas of these buried bitlines also decrease leading to an undesirable increase of their electrical resistance. A buried bitline with reduced resistance as well as a fabrication method thereof would be highly desirable.